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| Data Sheet No. PD60293 IRS254(0,1)(S)PbF LED BUCK REGULATOR CONTROL IC Description The IRS254(0,1) are high voltage, high frequency buck control ICs for constant LED current regulation. They incorporate a continuous mode time-delayed hysteretic buck regulator to directly control the average load current, using an accurate on-chip bandgap voltage reference. The application is inherently protected against short circuit conditions, with the ability to easily add opencircuit protection. An external high-side bootstrap circuit drives the buck switching element at high frequencies. A low-side driver is also provided for synchronous rectifier designs. All functions are realized within a simple 8 pin DIP or SOIC package. Features * 200 V (IRS2540) and 600 V (IRS2541) half bridge driver * Micropower startup (<500 A) * 2% voltage reference * 140 ns deadtime * 15.6 V zener clamp on VCC * Frequency up to 500 kHz * Auto restart, non-latched shutdown * PWM dimmable * Small 8-Lead DIP/8-Lead SOIC packages Packages 8-Lead PDIP IRS254(0,1)PbF 8-LeadSOIC IRS254(0,1)SPbF Typical Application Diagram VBUS L2 VOUT + RS1 RS2 DBOOT IC1 CVCC1 ROV1 CBUS2 CBUS1 DOV ROV2 CEN ENN VCC COM 1 2 8 7 6 5 VB IRS254(0,1) HO RG1 CBOOT DCLAMP CVCC2 M1 L1 IFB 3 4 VS LO M2 RG2 COUT VOUT - RF RCS ROUT CF COM EN DEN1 www.irf.com Page 1 IRS254(0,1)(S)PbF Alternate application circuit using a single MOSFET IRS254(0,1) www.irf.com Page 2 IRS254(0,1)(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO VIFB VENN ICC dV/dt PD RTHJA TJ TS TL Definition High-side floating supply voltage High-side floating supply offset voltage High-side floating output voltage Low-side output voltage Feedback voltage Enable voltage Supply current (Note 1) Allowable offset voltage slew rate Package power dissipation @ TA +25 C PD = (TJMAX-TA)/RTHJA Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8-Pin DIP) (8-Pin SOIC) (8-Pin DIP) (8-Pin SOIC) IRS2540 IRS2541 Min. -0.3 -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 -20 -50 ---------55 -55 --- Max. 225 625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 20 50 1 0.625 125 200 150 150 300 Units V mA V/ns W C/W C Note 1: This IC contains a zener clamp structure between the chip VCC and COM, with a nominal breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source greater than VCLAMP specified in the electrical characteristics section. Recommended Operating Conditions For proper operation the device should be used within recommended conditions. Symbol VBS VS VCC ICC TJ Definition High side floating supply voltage IRS2540 Steady state high-side floating supply offset voltage Supply voltage Supply current Junction temperature IRS2541 Min. VCC - 0.7 -1 -1 VCCUV+ Note 2 -25 Max. VCLAMP 200 600 VCLAMP 10 125 Units V mA C Note 2: Sufficient current should be supplied to VCC to keep the internal 15.6 V zener regulating at VCLAMP. www.irf.com Page 3 IRS254(0,1)(S)PbF Electrical Characteristics VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 F, TA=25 C unless otherwise specified. Symbol Definition VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis UVLO mode quiescent current Diesabled mode quiescent current Quiescent VCC supply current VCC supply current, f = 50 kHz VCC zener clamp voltage Min Typ Max Units Test Conditions Supply Characteristics VCCUV+ VCCUVVUVHYS IQCCUV IQCCENN IQCC ICC50k VCLAMP 8.0 6.5 1.0 --------14.6 9.0 7.5 1.2 50 1.0 1.0 2.0 15.6 10.0 8.5 2.0 150 2.0 2.0 3.0 16.6 V mA A VCC=6 V EN>VENTH+ IFB = 1 V Duty Cycle = 50% f = 50 kHz ICC = 10 mA V VCC rising from 0 V VCC falling from 14 V Floating Supply Characteristics IQBS0 IQBS1 VBSUV+ VBSUVILK Quiescent VBS supply current Quiescent VBS supply current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold Offset supply leakage current ----6.5 6.0 --1.0 2.0 7.5 7.0 1 2.0 3.0 8.5 V 8.0 50 A IRS2540:VB=VS=200 V IRS2541:VB=VS=600 V mA VHO = VS IFB = 0 V Current Control Operation VENNTH+ VENNTHV0.5 VIFBTH f ENN pin positive threshold ENN pin negative threshold 0.5 V voltage reference (die level test) IFB pin threshold Maximum frequency 2.5 1.7 490 455 --2.7 2.0 500 500 500 3.0 2.3 510 540 --kHz V mV Gate Driver Output Characteristics VOL VHL tr tf IO+/DT tLO,ON tLO,OFF tHO,ON tHO,OFF Low level output voltage (HO or LO) High level output voltage (HO or LO) Turn-on rise time Turn-off fall time Output source/sink short circuit pulsed current Deadtime Delay between VIFB>VIFBTH and LO turn-on Delay between VIFB www.irf.com Page 4 IRS254(0,1)(S)PbF Electrical Characteristics VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 F, TA=25 C unless otherwise specified. Symbol Watchdog timer tWD PWWD Definition Watchdog timer period LO pulse width Min ----- Typ Max 20 1.0 ----- Units Test Conditions s IFB =1 V Functional Block Diagram 8 DELAY LEVEL SHIFT PULSE FILTER & LATCH VB HO VS 7 6 IFB 3 1 UVLO UVN DELAY 15.6 V VCC LO 5 ENN 4 100 K 2V BANDGAP REFERENCE 0. 5 V Watchdog Timer20 S 1 S Pulse Generator 2 COM Values in block diagram are typical values Lead Assignment Pin Assignments VCC 1 8 VB Pin # Symbol 1 2 3 4 5 6 7 8 VCC COM IFB ENN LO VS HO VB Description Supply voltage IC power & signal ground Current feedback Disable outputs (LO=High, HO=Low) Low-side gate driver output High-side floating return High-side gate driver output High-side gate driver floating supply IRS254(0,1) COM IFB ENN 2 3 4 7 HO 6 5 VS LO www.irf.com Page 5 IRS254(0,1)(S)PbF STATE DIAGRAM www.irf.com Page 6 IRS254(0,1)(S)PbF Functional Description Operating Mode The IRS254(0,1) operates as a time-delayed hysteritic buck controller. During normal operating conditions the output current is regulated via the IFB pin voltage (nominal value of 500 mV). This feedback is compared to an internal high precision bandgap voltage reference. An on-board dV/dt filter has also been used to ignore erroneous transitioning. Once the supply to the IC reaches VCCUV+, the LO output is held high and the HO output low for a predetermined period of time. This initiates charging of the bootstrap capacitor, establishing the VBS floating supply for the high-side output. The IC then begins toggling HO and LO outputs as needed to regulate the current. HO is large enough to maintain a low ripple on IFB, Iout,avg can be calculated: Iout (avg ) = VIFBTH RCS (A) Fig.2 (A) Storing Energy in Inductor (B) Releasing Inductor Stored Energy (B) 50% 50% 50% t_HO_off t_HO_on DT1 DT2 Iout LO 50% 50% HO IFB IFBTH t_LO_on t_LO_off LO Fig.1 IRS254(0,1) Control Signals, Iavg=1.2 A Fig.3 IRS254(0,1) Time Delayed Hysterisis As long as VIFB is below VIFBTH, HO is on, modulated by the watchdog timer described below, the load is receiving current from VBUS, which simultaneously stores energy in the inductor, as VIFB increases, unless the load is open. Once VIFB crosses VIFBTH, the control loop switches HO off after the delay tHO,OFF. Once HO is off, LO will turn on after the deadtime (DT), the inductor releases the stored energy into the load and VIFB starts decreasing. When VIFB crosses VIFBTH again, the control loop switches HO on after the delay tHO,ON and LO off after the delay tHO,ON + DT. The switching continues to regulate the current at an average value determined as follows. When the inductance value The control method is based upon a free running frequency, in constrast to a more widely used fixed frequency regulation. This reduces the part count since there is no need for frequency setting components and also provides an inherently stable sytem, which acts as a current source. A deadtime of approximately 140 ns between the two gate drive signals is necessary to prevent a "shoot-through" condition. At higher frequencies, the switching losses become very large in the absence of this deadtime. The deadtime has been adjusted to maintain precise current regulation, while still preventing shoot-through. www.irf.com Page 7 IRS254(0,1)(S)PbF Watchdog Timer During an open circuit condition, without the watchdog timer, the HO output would remain high at all times and the charge stored in the bootstrap capacitor CBOOT would gradually discharge the floating power supply for the high-side driver, which would then be unable to fully switch on the upper MOSFET causing high losses. To maintain sufficient charge on the bootstrap capacitor, a watchdog timer has been implemented. In the condition where VIFB remains below VIFBTH, the HO output will be forced low after 20 s and the LO output forced high. This toggling of the outputs will last for approximately 1 s to maintain and replenish sufficient charge on CBOOT. Design Tip (DT 98-2), "Bootstrap Component Selection For Control ICs" at www.irf.com under Design Support Disable (ENN) Pin The disable pin can be used for dimming and opencircuit protection. When the ENN pin is held low, the chip remains in a fully functional state with no alterations to the operating environment. To disable the control feedback and regulation, a voltage greater than VENTH (approximately 2.5 V) needs to be applied to the ENN pin. With the chip in a disabled state, HO output will remain low, whereas the LO output will remain high to prevent VS from floating, in addition to maintaining charge on the bootstrap capacitor. The threshold for disabling the IRS254(0,1) has been set to 2.5 V to enhance immunity to any externally generated noise, or application ground noise. This 2.5 V threshold also makes it ideal to receive a drive signal from a local microcontroller. Dimming Mode To achieve dimming, a signal with constant frequency and set duty cycle can be fed into the ENN pin. There is a direct linear relationship between the average load current and duty cycle. If the ratio is 50%, 50% of the maximum set light output will be realized. Likewise if the ratio is 30%, 70% of the maximum set light output will be realized. A sufficiently high frequency of the dimming signal must be chosen to avoid flashing or "strobe light" effect. A signal on the order of a few kHz should be sufficient. The minimum amount of dimming achievable (light output approaches 0%) will be determined by the "on" time of the HO output, when in a fully functional regulating state. To maintain reliable dimming, it is recommended to keep the "off" time of the enable signal at least 10 times that of the HO "on" time. For example, if the application is running at 75 kHz with an input voltage of 100 V and an output voltage of 20 V, the HO "on" time will be 3.3 s (one-fourth of the period - see calculations below) according to standard buck topology theory. This will set the minimum "off" time of the enable signal to 33 s. HO LO Fig.4 Illustration of Watchdog Timer Bootstrap Capacitor and Diode The bootstrap capacitor value needs to be chosen so that it maintains sufficient charge for at least the approximately 20 s interval until the watchdog timer allows the capacitor to recharge. If the capacitor value is too small, the charge will dissipate in less than 20 s. The typical bootstrap capacitor is approximately 100 nF. The bootstrap diode should be a fast recovery or ultrafast recovery component to maintain good efficiency. Since the cathode of the bootstrap diode will be switching between zero and to the high voltage bus, the reverse recovery time of this diode is of critical importance. For additional information concerning the bootstrap components, refer to the Duty Cycle = V out 20V 100 = *100 = 20% Vin 100V 75kHz = 3.3s HOon time = 20% * 1 www.irf.com Page 8 IRS254(0,1)(S)PbF form the voltage clamp. The repetition of the spikes can be reduced by simply increasing the capacitor size. The two resistors form a voltage divider for the output, which is then fed into the cathode of the zener diode. The diode will only conduct, flooding the enable pin, when its nominal voltage is exceeded. The chip will enter a disabled state once the divider network produces a voltage at least 2.5 V greater than the zener rating. The capacitor serves only to filter and slow the transients/switching at the positive output terminal. The clamped output voltage can be determined by the following analysis. The choice of capacitor is at the designer's discretion. Vout = Enable Duty Cycle Relationship to Light Output 100 90 80 Enable Pin Duty Cycle 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 Percentage of Light Output Fig.5 Light Output vs Enable Pin Duty Cycle (2.5V + DZ )(R1 + R2 ) R2 EN DZ = Zener Diode Nominal Rated Voltage HO LO Fig.6 IRS254(0,1) Dimming Signals Open Circuit Protection Mode By using the suggested Vout voltage divider, R1 capacitor, and zener diode, the output IFB voltage can be clamped 3 at any desired value. In EN open-circuit condition 4 without output clamp, R2 the positive output terminal will float at the Fig.7 Open Circuit high-side input voltage. Protection Scheme Switching will still occur between the HO and LO outputs, whether due to the output voltage clamp or the watchdog timer. Transients and switching will be observed at the positive output terminal as seen in Fig. 8. The difference in signal shape, between the output voltage and the IFB, is due to the capacitor used to IRS2540/1 Fig.8 Open Circuit Fault Signals, with Clamp Under-voltage Lock-out Mode The under-voltage lock-out mode (UVLO) is defined as the state IRS254(0,1) is in when VCC is below the turn-on threshold of the IC. During startup conditions, if the IC supply remains below VCCUV+, the IRS254(0,1) will enter the UVLO mode. This state is very similar to when the IC has been disabled via control signals, except that LO is also held low. When the supply is increased to VCCUV+, the IC enters the normal operation mode. If already in normal www.irf.com Page 9 IRS254(0,1)(S)PbF operation, the IC does not enter UVLO unless the supply voltage falls below VCCUV--. Inductance Selection To maintain tight hysteretic current regulation the inductor and output capacitor COUT (in parallel with the LEDs) need to be large enough to maintain the supply to the load during tHO,ON and avoid significant undershooting of the load current, which in turn causes the average current to fall below the desired value. First, we are going to look at the effect of the inductor when there is no output capacitor to clearly demonstrate the impact of the inductor. In this case, the load current is identical to the inductor current. Fig. 9 shows how the inductor value impacts the frequency over a range of input voltages. As can be seen, the input voltage has a great impact on the frequency and the inductor value has the greatest impact at reducing the frequency for smaller input voltages. 425 375 add capacitance no longer has a significant effect on the operating frequency or current regulation, as can be seen in Figs. 13 and 14. 400 390 380 Iout (mA) 370 360 350 340 330 30 80 Vin (V) 130 180 470uH 680uH 1mH 1.5mH Fig.10 Current Regulation for Chosen Inductances Iout = 350 mA, Vout = 16.8 V 400 380 360 Frequency (kHz) 470uH 680uH 1mH 1.5mH Frequency (kHz) 340 320 300 280 260 240 220 200 470uH 680uH 1mH 1.5mH 325 275 225 175 30 80 Vin (V) 130 180 13 18 23 Vout (V) 28 33 Fig.9 Frequency Response for Chosen Inductances Iout = 350 mA, Vout = 16.8 V Fig.11 Frequency Response for Chosen Inductances Iout = 350 mA, Vin = 50 V Iout (mA) Fig. 10 shows how the variation in load current increases over a span of input voltages, as the inductance is decreased. Fig. 11 shows the variation of frequency over different output voltages and different inductance values. Finally Fig. 12 shows how the load current variation increases with lower inductance over a range of output voltages. The output capacitor can be used simultaneously to achieve the target frequency and current control accuracy. Fig. 11 shows how the capacitance reduces the frequency over a range of input voltage. A small capacitance of 4.7 F has a large effect on reducing the frequency. Fig. 12 shows how the current regulation is also improved with the output capacitance. There is a point at which continuing to 345 343 341 339 337 335 333 331 329 327 325 13 18 23 Vout (V) 28 33 470uH 680uH 1mH 1.5mH Fig.12 Current Regulation for Chosen Inductances Iout = 350 mA, Vin = 50 V www.irf.com Page 10 IRS254(0,1)(S)PbF 1000 0uF 4.7uF 10uF 22uF Frequency (kHz) 33uF 47uF 100 from the output needs to be implemented, as seen in Fig. 16. 10 30 50 70 90 110 Vin (V) 130 150 170 Fig. 13 Iout = 350 mA, Vout = 16.8 V, L = 470 H 400 350 300 Frequency (kHz) 250 200 150 100 50 0 0 10 20 30 40 50 Capacitance (uF) Fig. 15 Iout = 350 mA, Vin = 100 V, Vout = 16.85 V, L = 470 H, C out = 33 F 40V 100V 160V Fig. 14 I out = 350 mA, Vout = 16.8 V, L = 470 H The addition of the COUT increases the amount of energy that can be stored in the output stage, which also means it can supply current for an increased period of time. Therefore by slowing down the di/dt transients in the load, the frequency is effectively decreased. With the COUT capacitor, the inductor current is no longer identical to that seen in the load. The inductor current will still have a perfectly triangular shape, where as the load will see the same basic trend in the current, but all sharp corners will be rounded with all peaks significantly reduced, as can be seen in Fig. 15 VCC Supply Since the IRS245(0,1) is rated for 200 V (or 600 V), VBUS can reach values of this magnitude. If only a supply resistor to VBUS is used, it will experience extremely high power losses. For higher voltage applications an alternate VCC supply scheme utilizing the micro-power start-up and a resistor feed-back The resistance between VBUS and VCC supply should be large enough to minimize the current sourced directly from the input voltage line; value should be on the order of hundreds of k. Through the supply resistor, a current will flow to charge the VCC capacitor. Once the capacitor is charged up to the VCCUV+ threshold, the IRS254(0,1) enters the micro start-up regime and begins to operate, activating the LO and HO outputs. After the first few cycles of switching, the resistor connected between the output and VCC will take over and source all necessary current for the IC. The resistor connecting the output to the supply should be carefully designed according to its power rating. RS 2 = Vout - 15.6V 10mA PRS 2 _ Rated 2 PRS 2 = (10mA) 2 RS 2 Icc 10mA VBUS VCC 1 2 3 4 8 7 6 5 VB IRS254(0, 1) COM HO IFB VS ENN ENN LO COM Fig. 16 Alternate Supply Diagram www.irf.com Page 11 IRS254(0,1)(S)PbF www.irf.com Page 12 IRS254(0,1)(S)PbF 8-Lead SOIC Tape & Reel LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C E B A G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 www.irf.com Page 13 IRS254(0,1)(S)PbF ORDER INFORMATION 8-Lead PDIP IRS2540PBF 8-Lead PDIP IRS2541PbF 8-Lead SOIC IRS2540SPbF 8-Lead SOIC IRS2541SPbF 8-Lead SOIC Tape & Reel IRS2540STRPbF 8-Lead SOIC Tape & Reel IRS2541STRPbF The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com www.irf.com Page 14 |
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